Cadence扩展TSMC伙伴关系AI和HPC芯片设计

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Home » Cadence Expands TSMC Partnership for AI and HPC Chip Design Cadence has announced an expanded partnership with TSMC to deliver advanced capabilities for AI and HPC designers. Cadence has achieved tool certification for TSMC’s advanced A14 process, demonstrated an industry-leading UALink solution in TSMC N3P, and introduced new silicon-proven IP for N3P and N2P technologies. Through this partnership, the companies are enabling agentic AI chip and 3D-IC design flows across TSMC’s N3, N2, A16 and A14 process technologies, including TSMC 3DFabric support for wafer-scale systems with hundreds of chiplets. “Cadence’s partnership with TSMC continues to deliver breakthrough innovations that enable leading‑edge customers to accelerate their most advanced semiconductor designs,” said Chin‑Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With AI‑driven design flows, silicon‑proven IP and 3D-IC solutions, we’re helping customers achieve faster time to market and improved PPA on TSMC’s leading‑edge process technologies.” “TSMC, together with our Open Innovation Platform (OIP) partners like Cadence, is addressing the key demands of semiconductor development to achieve higher performance and energy efficiency in AI systems,” said Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC. “With broad collaboration on AI-based solutions, our longstanding partnership is further accelerating our mutual customers’ journey of expanding AI with leadership silicon.” Cadence’s digital full flow, signoff flow, and custom/analog flows are now certified for TSMC A16 and A14 process technologies. The digital full flow features the Innovus Implementation System, Cadence Cerebrus Intelligent Chip Explorer for DTCO and enhanced signoff tools including the Tempus Timing and ECO Solution, EMX Planar 3D Solver, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Pegasus Verification System, and the Liberate Characterization Portfolio and the enabled Genus Synthesis Solution. For custom and analog design, Virtuoso Studio solutions include design‑rule‑correct layout generation and automated design migration to TSMC A16 and A14, reducing iterations by up to 2.5X and improving first‑pass success for AI, HPC and mobile SoCs. On the IP front, UCIe-64G has been taped out on TSMC A14, LPDDR6 IP is in development, and a wide selection of HPC & AI memory IP and other protocols needed for compute chiplets have been prioritized for development. Artisan Foundation IP and mixed‑signal IP for TSMC A14 are also in development and are expected to be available in Q4 2026, including standard cells, GPIO, and Memory Compilers for HPC/AI and networking applications. N2P Certified Tool Flows and IP for Infrastructure AI and Physical AI Applications Cadence analog, digital, and signoff tool flows have been certified for TSMC N2P. The Virtuoso Layout Suite has added enhanced connectivity models providing a production-ready custom design environment for quicker design starts. Further, the certified flows will enable faster tape-outs and designer productivity. Taped-out N2P IP includes DDR5, LPDDR5, and PCIe 6.0, with PCIe 3.0 IP expected to tape out in Q4 2026. UCIe-64G IP on N2P silicon is in the testing lab and has been characterized on N3P. Expanded 3DFabric and TSMC-COUPE Support for Scaling to Hundreds of Chiplets Cadence solutions are enabled supporting TSMC SoW-X full design flow with hundreds of chiplets and millions of bumps. Also enabled is the design of 5X reticle‑size CoWoS‑L‑style advanced packages, and ability to integrate key technology components such as SoIC, eDTC, MIMCap, IVR, HBM logic base die, and substrate, using Integrity 3D-IC for system planning and assembly. A pre-simulation-driven, die-to-die auto-routing flow is now certified with the Cadence Allegro Substrate Router and the Cadence OmniRoute Advanced Interconnect Router, automatically deriving signal-inte