CoWoS-L继续领先AI通过2028年芯片包装技术

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Home » Packaging » CoWoS-L to Remain Leading AI Chip Packaging Technology Through 2028 Growing AI chip sizes are pushing advanced packaging beyond reticle limits, increasing adoption of CoWoS-L and competing EMIB technologies. Growing AI chip sizes and higher HBM integration are driving demand for larger 2.5D packages, with TSMC’s CoWoS-L expected to remain the main advanced packaging solution for AI chips through 2028, according to TrendForce. The research firm said NVIDIA’s high-end GPU shipments are expected to increase about 30% year over year in 2026, while AMD’s MI400 and MI450 accelerators are expected to add further demand from the second half of the year. Among cloud service providers developing custom AI accelerators, Google is expected to lead in shipment volume and growth in 2026, with TPU v7 as its main product. AWS is also expanding its custom silicon deployment, with Trainium v3 expected to enter broader use from the second half of 2026. Microsoft and Meta continue to rely more heavily on GPU-based systems. Most AI server chips have used TSMC’s CoWoS-S, which employs a silicon interposer to connect compute dies and HBM. As package dimensions and HBM counts increase, however, the silicon interposer is approaching reticle-size limitations. CoWoS-L addresses this constraint by incorporating high-speed silicon bridge dies into the interposer, allowing larger packages and greater flexibility in connecting compute dies and HBM. TrendForce said CoWoS-S can integrate two SoCs or chiplets with eight HBM modules and is expected to remain in use for designs such as Microsoft’s Maia 200. More complex configurations requiring additional compute dies and HBM are expected to move to CoWoS-L. NVIDIA and AMD have already adopted CoWoS-L for their AI accelerators. Among custom AI chips, Meta’s MTIA 400 uses the technology, while AWS and Microsoft are expected to adopt CoWoS-L in 2027. The larger interposer used by CoWoS-L increases packaging costs, while constraints on TSMC’s advanced packaging capacity are creating opportunities for Intel’s embedded multi-die interconnect bridge (EMIB) technology. EMIB reduces reliance on a large silicon interposer, potentially lowering packaging costs. Its performance, however, is constrained by the routing density of the package substrate. Intel has increased line/space and microbump capabilities to address these limitations and is developing EMIB-T, which incorporates through-silicon vias to shorten signal paths. TrendForce expects Google to adopt EMIB-T in 2027, while AWS is also testing EMIB. Despite the competition, the research firm expects CoWoS-L’s technology maturity and yield advantages to keep it as the mainstream advanced packaging technology for AI chips through 2028.