边缘隐藏的挑战AI设计

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As models evolve faster than silicon cycles, chip architects must balance flexible compute, data movement, and defense-in-depth security. The rapid buildout of the edge is forcing chip architects and design teams to rethink how they add AI to vertical market applications. The fundamental challenge is a mismatch in timelines, because engineering teams must design for AI models, workloads, and deployment requirements that inevitably will shift long after silicon decisions are locked in. Compounding this, real-world edge performance rarely depends on peak NPU TOPS. More often, it depends on memory bandwidth, latency, power budgets, security, and data movement. To keep pace with evolving models, architects are leaning heavily into flexibility — embracing heterogeneous compute, programmable data paths, expandable memory, secure field updates, and tight hardware-software co-design. But flexibility alone isn’t enough. AI introduces broad attack vectors across models, data, keys, firmware, and inference pipelines, so robust security must be architected into hardware from day one. At the same time, fragmented toolchains across runtimes and frameworks make hardware-aware optimization just as important as raw compute. This structural shift is redefining standard component boundaries. “CPUs are becoming more GPU-like as they try to do more and more parallel processing,” observed Rob Fisher, senior director of product management at Imagination Technologies . “NPUs are becoming more GPU-like as they try to become more flexible, and the convergence point is with the CPU, NPU, and GPU in the middle. We’re finding more customers are trying to hedge their bets against the future than trying to squeeze out every last drop of performance today. That means we’re no longer just looking at a GPU you can slot in that just does GPU-like things. This has system-level impacts on the whole SoC.” When designing edge applications with AI as a product feature, chip architects and design teams have many considerations. Hardware choices drive these broader architectural decisions, but the challenge reaches well beyond NPU TOPs. “AI model performance depends on architectural details for memory, latency, power, and security,” said Eduardo Montanez, vice president and head of PSOC Edge MCUs & Edge AI Solutions for Infineon’s IoT, Compute & Wireless Business. This is why the company’s edge microcontrollers include memory expandability, a low-latency architecture, and energy efficiency to enable battery-powered applications at the edge. They also include security features that are designed to protect data and software IP. AI applications at the edge are already challenging chip architects and design teams to keep up with rapid changes in models and workloads. “As new networks are continually popping up, any solution needs to be programmable to accommodate new networks and ever-changing activation functions and corresponding data types,” said George Wall, product marketing group director at Cadence . “At the same time, there are hard performance requirements that must also be met.” This makes hardware-software co-design increasingly important. “AI models, NPUs, memory hierarchy, and optimization techniques such as quantization, pruning, and distillation must be jointly optimized to achieve efficient deployment,” noted Niranjan Sitapure, group product manager for generative AI at Siemens EDA . The entire pipeline also must be optimized, because success depends on sensor ingestion, data preprocessing, inference, post-processing, and ongoing model lifecycle management. Ideally, chip architects and design teams would have a detailed view of what an edge application will do, including the models it will use, required performance, available memory, and power constraints, so they can design a chip for optimal PPA. “Unfortunately, that isn’t reality,” said Paul Karazuba, vice president of marketing, Silicon IP at Rambus . “Even compressed, the chip design cycl